Phase-Locked Frequency Generation and Clocking: Architectures and circuits for modern wireless and wireline systems (Materials, Circuits and Devices)

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Contents
About the editor
Part I: Basic architectures and system perspectives
	1 Evolution of monolithic phase-locked loops
		1.1 Overview
		1.2 Architectures and circuits
			1.2.1 PLL with PFD and charge pump
			1.2.2 PLL with ring VCO
			1.2.3 PLL with dual-path control
			1.2.4 Delay-locked loop
			1.2.5 Bang-bang PLL
			1.2.6 Delta-sigma fractional-N PLL
			1.2.7 Digital-intensive PLL
			1.2.8 LC VCO
			1.2.9 Frequency divider
		1.3 Application aspects
			1.3.1 Synchronization
			1.3.2 Clock generation
			1.3.3 Clock-and-data recovery
			1.3.4 Frequency synthesis and modulation
		1.4 Summary
		Acknowledgments
		References
	2 Fractional-N frequency synthesis
		2.1 Basics
			2.1.1 Fractional-N operation
			2.1.2 Excess phase noise
			2.1.3 Delta-sigma fractional-N PLLs
				2.1.3.1 Model of excess phase in a delta-sigma fractional-N PLL
			2.1.4 Applications
			2.1.5 Challenges
		2.2 Digital delta-sigma modulator design
			2.2.1 Modulator order
			2.2.2 DDSM architecture
			2.2.3 Dithering
		2.3 Circuit design issues
			2.3.1 PFD and CP
				2.3.1.1 Increased charge pump noise contribution
				2.3.1.2 PFD/CP non-linearity
			2.3.2 Multi-modulus frequency dividers
		2.4 Wideband fractional-PLLs
			2.4.1 Phase noise cancellation
				2.4.1.1 Handling high dynamic range of cancellation path
				2.4.1.2 Matching the main and cancellation paths
			2.4.2 Multi-phase fractional-N PLLs
		2.5 Conclusion
		References
	3 Clock data recovery: a system perspective
		3.1 Basic communication system
		3.2 Clock data recovery
			3.2.1 Phase detector
			3.2.2 Closed-loop response
			3.2.3 Latency considerations
			3.2.4 Update rate
			3.2.5 Jitter tolerance
		3.3 Timing function selection
			3.3.1 Alexander phase detector
			3.3.2 Mueller-Müller phase detector
			3.3.3 Timing function analysis
		3.4 Eye diagram
			3.4.1 Statistical eye construction
			3.4.2 Tri-bit eye diagram
		3.5 An optimization example
		3.6 Conclusion
		References
	4 Silicon-based THz frequency synthesizers with wide locking range
		4.1 Architecture of the THz frequency synthesizer
		4.2 Triple-push VCO with CAV
		4.3 Three-phase injection locked divider (÷4)
		4.4 Integration and layout of VCO and divider
		4.5 Measurement
		4.6 Conclusion
		References
Part II: Digital-intensive phase-locked loops
	5 Time-to-digital converters
		5.1 Introduction
		5.2 Time–digital conversion basis
			5.2.1 Time–digital conversion key parameters
				5.2.1.1 Basic structural parameters
				5.2.1.2 Performance specifications
		5.3 Time–digital converter architectures
			5.3.1 Counter-based TDC
			5.3.2 Analog-to-digital conversion-based TDC
			5.3.3 Flash (single delay line) TDC
			5.3.4 Vernier delay line TDC
			5.3.5 Vernier ring TDC
			5.3.6 Oversampling gated ring oscillator (GRO) TDC
			5.3.7 Time amplifier-based TDC
		5.4 Advanced time-to-digital conversion techniques
			5.4.1 Linearity issues associated with 2-D Vernier TDC
			5.4.2 Spiral comparator array for 2-dimensional Vernier TDC
			5.4.3 Linearization improvement techniques
				5.4.3.1 Delay interpolation of unit delay cells
				5.4.3.2 2-D comparator array folding error randomization
				5.4.3.3 TDC delay calibration
		5.5 TDC implementation examples
			5.5.1 TDC architecture and circuit implementation
			5.5.2 Experiment results of the proposed TDC
		References
	6 Bang-bang digital PLLs for wireless systems
		6.1 Analysis of digital PLLs
			6.1.1 Standard TDC
			6.1.2 Moving to BB operation
		6.2 Fractional-N frequency synthesis
		6.3 Fast lock in BB PLLs
		6.4 Automatic bandwidth regulation
		6.5 Practical implementations and measurements
		6.6 Conclusions
		References
	7 Hybrid PLLs
		7.1 Introduction: analog and digital PLL considerations
		7.2 Hybrid VCO control with continuous tuning
		7.3 Frac-N noise cancellation in a digital-friendly technology
		7.4 Conclusion
		References
	8 Spur mitigation techniques for DPLL architecture
		8.1 Introduction
		8.2 The impact of spurious tones
			8.2.1 Specification of spurious performances in a wireless system
			8.2.2 Specification of spurious performances in a wireline system
		8.3 The generation of DPLL spurs
			8.3.1 Internal spurs due to fractional-N operation
			8.3.2 Internal spurs due to integer-N operation
			8.3.3 External spurs due to interferences
		8.4 DSP-assisted spur mitigation techniques leveraging the adaptive filter algorithm
			8.4.1 Adaptive spur mitigation algorithm
			8.4.2 I/Q correlator: minimization of residue error energy
			8.4.3 Convergence of the spur mitigation scheme
		8.5 Design example
			8.5.1 DPLL with a direct spur mitigation technique
				8.5.1.1 Overall DPLL architecture
				8.5.1.2 Feedforward multi-tone spur cancellation scheme
				8.5.1.3 Derivation of the cancellation algorithm
				8.5.1.4 Integer and fractional delay
				8.5.1.5 Complete feedforward loop and adaptability
				8.5.1.6 Implementation highlight: integer and fractional averaging scheme
				8.5.1.7 Modular extension: cascaded cancellation loops
				8.5.1.8 Measurement results
			8.5.2 DPLL with a dither-based spur mitigation technique
				8.5.2.1 Overall DPLL architecture
				8.5.2.2 Dither noise cancellation scheme
				8.5.2.3 Implementation highlight: dither noise cancellation loop
				8.5.2.4 Measurement results
		8.6 Conclusion
		References
	9 Fully synthesized digital PLL
		9.1 Design process
			9.1.1 Digital-compatible design flow
			9.1.2 Hardware description language-based circuit design
		9.2 PLL architecture
			9.2.1 Proposed PLL architecture
		9.3 Design example I: injection-locked PLL with an interpolative phase-coupled oscillator
			9.3.1 Interpolative phase-coupled oscillator
			9.3.2 Current-output DAC converter
			9.3.3 Standard-cell-based varactor
			9.3.4 Gated edge injection
			9.3.5 Measurement results
		9.4 Design example II: injection-locked PLL with bang-bang phase detector-based frequency and phase calibration
			9.4.1 PLL architecture and noise analysis
			9.4.2 Highly linear DCO with self-clocked nonoverlap update
			9.4.3 Fully symmetrical low-offset MUX and SS-BBPD design
			9.4.4 Measurement results
		9.5 Summary and conclusion
		References
	10 Ultra-low-power ADPLL
		10.1 Introduction
		10.2 Requirements and architecture considerations for low-power ADPLL
			10.2.1 Phase noise and spur considerations for IoT applications
			10.2.2 Low-power fractional ADPLL architectures
			10.2.3 DTC for low-power ADPLL
				10.2.3.1 Variable SR (variable-slope) DTC
				10.2.3.2 Variable starting voltage (constant-slope) DTC
				10.2.3.3 Variable threshold (ramp division) DTC
		10.3 Proposed ULP ADPLL architecture
			10.3.1 System overview
			10.3.2 Low-power highly linear DTC
				10.3.2.1 Concept operation
				10.3.2.2 Nonlinear sources and circuit implementations
				10.3.2.3 Simulation results
			10.3.3 Narrow-range high-resolution TDC
			10.3.4 Coarse DPLL
		10.4 Measurement results
		10.5 Conclusion
		References
Part III: Low-noise frequency generation and modulation
	11 Integrated LC oscillators
		11.1 LC oscillator design challenges in RF transceivers
			11.1.1 WiFi, Bluetooth low energy, and Internet of things
				11.1.1.1 WiFi IEEE 802.11
				11.1.1.2 Bluetooth low energy
				11.1.1.3 Narrowband IoTs
			11.1.2 4G Long-term evolution and 5G NR
		11.2 LC oscillator principles of operation
			11.2.1 Oscillator start-up condition, frequency tuning, and phase noise
				11.2.1.1 Start-up condition
				11.2.1.2 Frequency tuning
				11.2.1.3 Phase noise
			11.2.2 Topology comparison of NMOS VCO and CMOS VCO
		11.3 Wideband LC oscillator
			11.3.1 Switchable inductor oscillator design
			11.3.2 Multi-resonator oscillator design
			11.3.3 Dual-mode oscillator design
		11.4 Low-noise and low-power LC oscillator
			11.4.1 Coupled oscillator
			11.4.2 Class C oscillator
			11.4.3 Class F Oscillator
		References
	12 Mm-wave and sub-THz CMOS VCOs
		12.1 Introduction
		12.2 Magnetic tuning technique
			12.2.1 Coarse magnetic tuning
			12.2.2 Fine magnetic tuning
				12.2.2.1 Fine magnetic tuning with variable capacitor
				12.2.2.2 Fine magnetic tuning with variable resistor
				12.2.2.3 Fine magnetic tuning with variable transistor
			12.2.3 Coarse and fine magnetic tuning
			12.2.4 Fine magnetic tuning with split transformer
		12.3 Design prototypes
			12.3.1 Coarse magnetic tuning multi-mode VCO
			12.3.2 Coarse and fine magnetic tuning DB-VCO
			12.3.3 Fine magnetic tuning split transformer-based VCO
		12.4 Conclusion
		References
	13 Ultra-low phase noise ADPLL for millimeter wave
		13.1 Evolution of mm-wave frequency synthesizer architectures
		13.2 Mm-wave ADPLL with implicit frequency tripling
		13.3 Oscillator with implicit frequency multiplication
			13.3.1 Third-harmonic boosting
			13.3.2 Suppression of 1/f3 noise in oscillators
			13.3.3 DCO capacitor bank design
		13.4 The 20-GHz component suppression
		13.5 Phase detection
		13.6 Digital LF
		13.7 Experimental results
			13.7.1 Open-loop test
			13.7.2 Close-loop test
		References
	14 DTC-based subsampling PLLs for low-noise synthesis and two-point modulation
		14.1 Fractional-N subsampling PLL enabled by a DTC
			14.1.1 Limitations introduced by the DTC and their mitigation on the system level
				14.1.1.1 DTC resolution
				14.1.1.2 DTC gain error
				14.1.1.3 DTC nonlinearity
				14.1.1.4 DTC phase noise
		14.2 Subsampling PLL-based phase modulator enabled by a DTC
			14.2.1 Two-point modulation
			14.2.2 Limitations of the technique and their mitigation on the system level
		14.3 Analog circuits
			14.3.1 Digital-to-time converter
			14.3.2 Subsampling loop
			14.3.3 VCO implementation
			14.3.4 Frequency acquisition
		14.4 Experimental results
		14.5 Conclusion
		References
	15 Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering
		15.1 Introduction
		15.2 Hybrid two-point modulation with embedded FIR filter
			15.2.1 Semi-digital PLL with hybrid FIR filtering
			15.2.2 Dedicated high-pass modulation path with FIR-embedded 1-bit control
			15.2.3 Linear model of the hybrid loop two-point modulator
			15.2.4 Gain and delay mismatch analysis and calibration
		15.3 Circuit implementation
		15.4 Implement results
		15.5 Conclusion
		References
Part IV: Clock-and-data recovery and clocking
	16 An overview of CDR in ultra-high-speed wireline transceivers
		16.1 Introduction
		16.2 CDR in SerDes
		16.3 Requirements and approaches for CDR in ultra-high-speed wireline transceivers
		16.4 CDR for NRZ modulation scheme
		16.5 CDR for PAM-4 modulation scheme
		16.6 Conclusion
		References
	17 Clock and data recovery for optical links
		17.1 Prior art of BMCDR
		17.2 BMCDR with jitter filtering
		17.3 Burst mode CDR circuit implementation
			17.3.1 Lock detector
			17.3.2 Reconfigurable loop filter
			17.3.3 Selective gating VCO
			17.3.4 An 1/5-rate phase detector
			17.3.5 Dual-mode loop filter
			17.3.6 Burst mode CDR experimental results
		17.4 Fully integrated optical receiver with baud-rate CDR
		17.5 Architecture of optical receiver with baud-rate CDR
		17.6 Circuit implementation of optical receiver with baud-rate CDR
			17.6.1 Current amplifier
			17.6.2 Comparator
			17.6.3 Baud-rate PD
			17.6.4 Charge mode logic subtractor
			17.6.5 Hybrid loop filter and phase interpolator
			17.6.6 Experimental results of optical receiver with baud-rate CDR
		17.7 Conclusion
		References
	18 Digital clock and data recovery circuits
		18.1 Introduction
		18.2 Design and analysis of digital CDR
			18.2.1 Bang-bang phase detector (BBPD)
			18.2.2 Digital loop filter (DLF)
			18.2.3 Digital-to-analog converter
			18.2.4 Voltage controlled oscillator
			18.2.5 Noise analysis of a digital CDR
				18.2.5.1 Design example
		18.3 Design techniques for improving standard digital CDR
			18.3.1 Low-speed digital loop filter
			18.3.2 Digital frequency control in oscillators
			18.3.3 Digitally controlled oscillator (DCO)
			18.3.4 Decoupling JTRAN and JTRACK bandwidth in CDR
		18.4 Case study I: digital CDR with decoupled JTRAN and JTRACK
			18.4.1 A 5 Gb/s digital CDR using PRPLL
				18.4.1.1 Linear analysis of PRPLL-based digital CDR
		18.5 Case study II: A wide range digital clock and data recovery
			18.5.1 A 4–10 Gb/s digital clock and data recovery
			18.5.2 Fractional-N PLL-based DCO
			18.5.3 Digitally controlled delay line
			18.5.4 Linear analysis of a wide range CDR
		References
	19 Spread spectrum clock generator: a low-cost EMI solution
		19.1 Methods for electromagnetic interference (EMI) reduction
		19.2 Spread spectrum clock generation (SSCG): a cost-effective EMI solution
		19.3 Design approaches for SSCG
			19.3.1 PLL-based SSCG
				19.3.1.1 Analog PLL
				19.3.1.2 Digital PLL
			19.3.2 Delay-line-based SSCG
			19.3.3 FLL-based SSCG
		19.4 Methodologies for the SSC modulation profile
			19.4.1 Sinusoidal modulation profile
			19.4.2 Triangular modulation profile
			19.4.3 PLL-bandwidth-compensated triangular modulation
			19.4.4 Hershey–Kiss modulation profile
			19.4.5 Newton–Raphson modulation profile
			19.4.6 Piecewise-linear modulation profile
			19.4.7 Random modulation profile
			19.4.8 Nested modulation profile
		19.5 Conclusions
		References
	20 High-performance CMOS clock distribution
		20.1 Introduction
			20.1.1 Sources of jitter in clock distribution
			20.1.2 CMOS clocking for broadband clock distribution
		20.2 Power supply induced jitter (PSIJ) in the CMOS inverter
			20.2.1 Jitter sensitivity
			20.2.2 Jitter induced by common-mode and differential supply noise
			20.2.3 PSIJ accumulation
		20.3 Random jitter generation in the CMOS inverter
			20.3.1 Random jitter trend
		20.4 Jitter generation in global clock distribution
			20.4.1 Model of a CMOS inverter driving a low-loss transmission line
			20.4.2 Design of CMOS clock distribution with low jitter generation
			20.4.3 Example: jitter generation in 16 nm CMOS clock distribution
				20.4.3.1 PSIJ
				20.4.3.2 Random jitter
		20.5 Jitter amplification
			20.5.1 Jitter impulse response (JIR) and jitter transfer function (JTF)
			20.5.2 JIR and JTF for a cascade of clock buffers
			20.5.3 Design of CMOS clock distribution with low jitter amplification
		20.6 Summary
		References
Part V: Advanced clock/frequency generation
	21 Sub-sampling PLL techniques
		21.1 Classical charge pump PLL
		21.2 PLL figure-of-merit
		21.3 Sub-sampling PLL
		21.4 Power and spur reduction techniques for sub-sampling PLL
		21.5 Fractional-N sub-sampling PLL
		21.6 Digital sub-sampling PLL
		21.7 Discussion
		References
	22 PLLs with nested frequency-locked loop
		22.1 VCO noise reduction using reference-less FLL
			22.1.1 Basic concept
			22.1.2 Implementation and simulation
		22.2 Frequency-locked loop based on a switched capacitor feedback
			22.2.1 Basic concept
			22.2.2 Loop dynamics
			22.2.3 Noise analysis
			22.2.4 Circuit implementation
		22.3 A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop
			22.3.1 Motivation
			22.3.2 Wide bandwidth noise suppression loop (NSL)
			22.3.3 PLL with noise suppressed VCO
			22.3.4 Experimental results
		22.4 Conclusions
		References
	23 Time amplified charge pump PLL
		23.1 Noise of a digital charge-pump PLL
			23.1.1 Noise induced by dead-zone cancellation
			23.1.2 Noise induced by static phase error
			23.1.3 Noise transfer function of a charge pump
		23.2 Time amplified PLL
		23.3 Low-noise time amplifier
		23.4 Self-regulated and self-temperature compensation ring oscillator
		23.5 Ring oscillator-based TAPLL
		23.6 Measurements of ring TAPLL
		References
	24 Multiplying DLLs
		24.1 Introduction
		24.2 Advanced frequency-tracking loop
		24.3 Wideband multiplexed RVCO and frequency tuning scheme
		24.4 Phase noise analysis
		24.5 Performance comparison
		References
	25 Wideband PLLs
		25.1 Wideband integer-RF synthesizer
		RF synthesizer
			25.1.1 PLL bandwidth limitations
			25.1.2 Proposed integer-wideband PLL
			wideband PLL
				25.1.2.1 Type-I PLL with sampling filter
				25.1.2.2 MSSF transfer function
				25.1.2.3 Stability considerations
				25.1.2.4 Closed-loop behavior
				25.1.2.5 Acquisition range
			25.1.3 Phase noise considerations
				25.1.3.1 V3CO phase noise
				25.1.3.2 PD and MSSF phase noise
			25.1.4 Spur reduction
				25.1.4.1 Harmonic trap design
				25.1.4.2 Notch calibration
			25.1.5 Experimental results of integer-synthesizer
		25.2 Wideband fractional-RF synthesizer
		RF synthesizer
			25.2.1 Background
			25.2.2 Proposed noise suppression method
				25.2.2.1 Basic idea
				25.2.2.2 FIR implementation
				25.2.2.3 Filter frequency response
				25.2.2.4 Effect of nonidealities
			25.2.3 Proposed synthesizer architecture
			25.2.4 Design considerations
				25.2.4.1 Nonlinearity issues
				25.2.4.2 Delay line implementation
				25.2.4.3 PD nonmonotonicity
				25.2.4.4 Overall phase noise
			25.2.5 Experimental results of fractional-synthesizer
		References
Index
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